TVS07RF-25-11B_Datasheet PDF

 人参与 | 时间:2021-06-20 03:47:09

Of 1,000 Cyclone customers to date, 250 are first-time Altera customers, Daane said, leading to company to believe the product line is taking market share away from ASIC and standard product suppliers.

PlanAhead also has a manual or automatic physical block-sizing and placement feature, along with a clock I/O and clock-region-planning feature.

TVS07RF-25-11B_Datasheet PDF

A design team leader could also use the tool to chop a design into several blocks, assign the blocks to various designers in a group, then reassemble them in the PlanAhead environment, Kreiter said. Users can place unfinished blocks in a design before all the blocks have been assembled to get an early jump on a layout.

PlanAhead's design analysis capabilities address timing, connectivity, utilization, I/Os, clock regions and carry chains. Power and other analysis capabilities will be added soon, the company said.

Kreiter said that on a recent design project, a beta user of PlanAhead was able to shrink the size of nonessential blocks in a design that had a 101 percent utilization rate-requiring a second FPGA-yielding a device with a 96 percent utilization rate, while also meeting performance goals.

TVS07RF-25-11B_Datasheet PDF

This couldn't be done with even the best FPGA physical synthesis tools,” he said. Those tools flatten out a design and then run physical synthesis on the entire flattened design. They can take days to finish a million-gate FPGA design. Our flow allows users to pinpoint those trouble areas and optimize them to cut down on overall design time.”

PlanAhead currently does not have a back-annotation capability, Kreiter said. The tool generates reports that indicate a design's problem areas, for example, but does not backtrack to the RTL to pinpoint where in the code the problems cropped up. But Hier Design hopes to have such a feature in a future release, Kreiter said. The company also plans to add some physical synthesis capability, or to link to an established physical synthesis tool, giving designers an ability to resynthesize problem areas in a design.

TVS07RF-25-11B_Datasheet PDF

Synplicity Inc.'s Amplify FPGA physical synthesis tool, for example, can perform local synthesis, which spares designers from resynthesizing an entire design.

Hier Design is charging $25,000 for a one-year subscription license to PlanAhead.

Simultaneously, the system's main memory accumulates milliseconds of data at rates to 500 ps. The two memories are then time-correlated automatically at any sample point.

The result is that you get to view an event's placement, such as a glitch or a clock edge, to a resolution of 125 ps, all while maintaining a longer-term record of the data that surrounds it. Conventional sampling proceeds at clock rates up to 500 ps, while MagniVu typically samples at 125 ps.

In summary, MagniVu timing is 125 ps (8 GHz), with its storage rate adjustable to 250 ps, 500 ps, 1 ns, and 2 ns. The timing memory depth is 16 kbits/channel, with adjustable trigger position. Deep memory timing resolution is 500 ps, 1 ns, and 2 ns to 50 ms, for quarter/half/full channels. Deep memory timing memory depth (quarter/half/full channels with timestamps and with or without transitional storage) is 2 Mbits, 1 Mbit, 512 kbits, 8/4/2 Mbits, and 32/16/8 Mbits/channel.

How Much?

Tek's press statement doesn't mention price, but it's a spec that is really telling. The new Model TLA5201, for starters, can cost as little as $9200, depending on options. It's a 32-channel analyzer (two channels are clock channels).

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