人参与 | 时间:2021-06-20 03:34:15

Andy Lanfear, European DSP director for ADI, says the processor runs 16 or 32bit instructions and has multi-issue 64bit instructions that perform DSP and MCU operations simultaneously. For video and similar applications, the DSP unit can process data in 8bit chunks as a single-instruction, multiple-data (SIMD) unit.

San Jose, Calif. – Hynix Semiconductor Inc. (formerly Hyundai Electronics Industries) has added two 32-Mbit, low-voltage flash memories to its portfolio. With access times as low as 70 nanoseconds, the HY29DS322/323 and HY29LV320 can support emerging cell phone features such as Web browsing and voice recognition. The parts build on Hynix's current lineup of 2- to 8-Mbit 5-volt, and 16-Mbit 2- and 3-V, flash memories.

Sam Young, vice president of marketing for Hynix's Flash Memory Business Unit, said the new devices are aimed at applications requiring cost-effective 3-V and 2-V 32-Mbit solutions. They leverage the company's DRAM technology and will be built in its DRAM fabrication facilities. Our vast manufacturing capacity gives us a significant advantage over our competitors by allowing us to cost-effectively accommodate high-volume customer orders,” Young said.


Built on 0.25-micron lithography, each device provides 32 Mbits of nonvolatile storage and incorporates a triple-well channel erase flash technology developed by Hynix. An accelerated-programming mode is said to cut programming time by up to 40 percent, and a secured sector provides anticloning protection.

The HY29DS322/323 device reads, programs and erases over an operating voltage range of 1.8 to 2.2 V and features a dual-bank, simultaneous read/write architecture. It is available in 100-, 110- and 120-ns access time versions and can be configured for 4-Mbit x 8 or 2-Mbit x 16 operation.

The HY29LV320 is configured as 2 Mbits x 16, but is pin-compatible with similar 32-Mbit (x 8 and x 16) products. It's also compatible with (and is a density upgrade for) the 16-Mbit HY29LV160 and equivalents. The HY29LV320 operates from 2.7 to 3.6 V and is available in 70-, 80-, 90- and 120-ns access time versions.


The dual-bank architecture divides the chip into two banks of memory sectors that can perform independent operations. The design permits simultaneous read and write operations so that, for example, the host system can program or erase in one bank while simultaneously reading from any sector in the other bank, with zero latency between read and write operations. The ability to store code in one bank and data in the other is said to reduce the complexity of the operating code and eliminate the need for additional memory, as required in some older designs.

The secured sector can be locked at the factory or by customers. A corresponding secured indicator bit is permanently set to 1 if the part is factory locked or 0 if it is customer-locked. Thus, customer-lockable parts cannot be used to replace factory-locked parts, and telephones, for example, can be programmed with a unique ID number.


Hynix said its triple-well channel erase technology enables a memory cell size reduction of 10 to 20 percent over other flash devices at the same lithography. Channel length is reduced by about 20 percent. Fewer processing steps are needed, Hynix said, enhancing both endurance and data retention.

The HY29DS322/323 and HY29LV320 are available in 48-pin TSOP and 48-ball, 7.25 x 12-mm FBGA packages. Both devices comply with Jedec standards and are pinout and software compatible with single-power-supply flash device requirements. They also comply with the Common Flash Memory Interface specification, in which flash parameters are stored directly on the device, so the software driver can use different kinds of flash products.

•William Trevelyan Thomas & Richard O'Brien (both 14)Radley College, Abingdon, Oxon.A parcel box which automatically locks when a parcel is left inside.

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